This invention relates to semiconductor fabrication technology and products and specifically to the production of an insulated gate, vertical MOSgated transistor (xe2x80x9cMOSFETxe2x80x9d) using a mesa-type buried gate.
MOSgated devices are well known and include such devices as power MOSFETS, IGBTs, gate controlled thyristors and the like. In these devices, a source and drain layer are connected by a channel layer. A MOSgate forms a depletion region in the channel layer thereby allowing or preventing movement of carriers through the channel from the source to the drain.
In such devices, the gate and the channel region are either lateral or vertical relative to the plane of the channel. So called trench devices employ a vertical channel. Generally, this requires plural spaced narrow deep trenches into the semiconductor device substrate. A gate oxide lines the walls of the trench and the trench is then filled with a conductive polysilicon gate electrode filler.
Trench type MOSgated devices and have a low gate capacitance which is very useful in many low voltage applications. However, their fabrication is difficult and expensive, particularly due to the need to etch the deep trenches and fill them with a polysilicon gate filler. This process is complicated by the need for plural mask steps which must be aligned with great accuracy.
Therefore, there exists a need in the art for a method of inexpensively manufacturing a MOSgated device which does not require etching deep, narrow trench in silicon.
In accordance with the invention, a MOSgated device, such as a MOSFET, is formed by first depositing a conductive polysilicon layer atop and insulated from a silicon substrate and then etching away portions of the polysilicon thereby leaving polysilicon mesa-type structures which will act as gate structures. A gate oxide is then formed along the vertical sides of the polysilicon mesa structures. The space between the polysilicon mesas is then filled with epitaxially deposited silicon (which defines the channel regions) and their tops receive source regions and are enclosed by an insulation oxide. Source contents are then connected to the source regions and channel regions and a drain contact is connected to the bottom of the substrate. Thus, with the novel fabrication process of the invention, a novel MOSgated device can be formed with simple, well known process steps etching the polysilicon layer and not the silicon. Moreover, the technique of the invention only requires the use of only three masks with no critical alignment thus reducing cost and increasing reliability of the process.